Constructing an Application Specific Integrated Circuit (ASIC) is a process that involves many variables. Some of the variables are fairly consistent for the entire manufacturing process. Some variables vary from lot to lot but are consistent across a single lot of wafers. Still other variables vary from wafer to wafer but are consistent across a chip. Finally, some of the variation can occur within a single chip.
Examples of variables that can occur on a single chip include small variations in the mask, imperfection in optical proximity correction, and etch variations. Additionally, many of these variations can occur over a very small area. Consider, for example, a string of buffers that are all placed in a row. The gates in the middle of the string all have the same structures on each side, but the gates at the ends of the string are adjacent to the different features that may cause different variations in the etching process.
The many variables involved in the manufacturing process means the gate delay of a cell on a chip is actually a Gaussian distribution with a mean and standard deviation determined by the cell design and these many variables. A randomly chosen instance of a cell on a randomly chosen chip could be running at any point within that Gaussian distribution. Fortunately, timing analysis does not need to directly verify the chip's operation at every point in the distribution. Instead, if a design is shown to work at both the best case corner and the worst case corner, it is assumed to work at any corner in between.
Signal speeds associated with integrated circuit devices may be subject to both inter-chip variation and across-chip variation. Inter-chip variation, or differing speeds among integrated circuit devices in a system, has been a noted concern in the integrated circuit industry. As a result, various techniques have been developed for determining and compensating for inter-chip variation. However, across-chip variation, or differing signal path speeds in an individual integrated circuit device, is a relatively new concern for ASIC vendors and fabricators.
In order to determine across chip variation of signal paths of an integrated circuit device, simulated timing delays of the signal paths may be modeled with the use of a timing analysis tool. In modeling signal path delays, ASIC vendors and fabricators typically provide “best-case fast” and “worst-case slow” simulated timing delay models. For example, cells in a signal path will never be faster than the best-case fast model, or slower than the worst-case slow model. The determined across chip variation factor may be added to a signal path of the integrated circuit device in various ways, which are known to those skilled in the art.
As the size and complexity of an integrated circuit device increases, the resulting magnitude of across chip variation also increases. For example, a 20×20 millimeter chip with 5000 cell rows has an increased chance of having cells in the integrated circuit device operating at different speeds. A larger chip also has an increased chance of its signal paths being affected by process, voltage, temperature (PVT) factors, which may vary across the surface of an integrated circuit device.
Commonly, in order to determine an across chip variation factor for each signal path, the timing analysis tool is run at a single worst case PVT point. However, because PVT factors vary across the integrated circuit device, using an across chip variation factor computed from a single PVT point is unduly pessimistic, and can significantly increase project time, and thus development costs. Much of the delay resulting in across chip variation depends on the distances between the cells involved; for example, there is less of a delay if the cells are close together, more if they are far apart. Assuming a worst case variation of PVT factors for purposes of fabrication, as described above, may lead to signal path delays large enough to seriously disrupt an ASIC project schedule. This becomes more challenging with ASICs containing voltage islands containing independently powered circuits.
In an ASIC test environment, test site hardware is used to build and measure circuits and to correlate ASIC models to the hardware, including models for timing (performance), dynamic power and static power. A method conventionally used to isolate the IP for measurements is to build the experimental circuits inside an independently powered voltage island on the test site chip, isolating specific circuits from the chip logic/power supply. This enables verification ensuring that timing, dynamic/static power and leakage rules are met and data is bounded by limits. Additionally, temperature and voltage sensitivities may be characterized across multiple process windows as well as characterizing voltage island performance and leakage vs. four-corner PSRO (located in each corner of a chip) mean performance over complete process window coverage (Ion, VT, Leff).
However, there is presently no way to evaluate the effects of the local environment difference inside the voltage island. Local variations in performance, voltage, temperature, and voltage island perimeter density (environment, topology) may affect the performance, power and leakage of the design. There is a need, therefore, to correlate PSRO and specific integrated circuits and/or track voltage island to chip variation.